State detection circuit for anti-fuse memory cell, and memory

A memory, comprising a state detection circuit for an anti-fuse memory cell, wherein the state detection circuit comprises:

• an amplifier, which has a first input terminal connected with a first reference voltage, a second input terminal connected with a first node, and an output terminal connected with a second node;
• an anti-fuse memory cell array, which comprises a plurality of anti-fuse memory cell sub-arrays, wherein bit lines of the plurality of anti-fuse memory cell sub-arrays are connected with the first node, and word lines of the plurality of anti-fuse memory cell sub-arrays are connected with a controller, and each of the anti-fuse memory cell sub-arrays comprises a plurality of anti-fuse memory cells;
• a first switch element, which has a first terminal connected with a power supply, a second terminal connected with the first node, and a control terminal connected with the second node;
• a second switch element, which has a first terminal connected with the power supply, a second terminal connected with a third node, and a control terminal connected with the second node;
• a third switch element, which has a first terminal connected with the third node, a second terminal that is grounded, and a control terminal connected with the controller;
• and
• a comparator, which has a first input terminal connected with the third node, and a second input terminal connected with a second reference voltage.