Methods and systems for address based transaction filters for on-chip communications fabrics
AssigneePensando Systems Inc.
InventorMichael Brian GALLES
Life of this patent
Estimating the term…
Abstract
A configurable transaction filtering and logging circuit for on-chip communications within a semiconductor chip can store filter patterns. The filter patterns can include an address range filter pattern. The circuit can monitor transactions carried by an on-chip connection fabric. The transactions can be configured to transfer data between a first core circuit and a second core circuit that are also implemented on the semiconductor chip. The circuit can execute one of a set of actions in response to detecting a transaction that matches one of the filter patterns. One of the actions can be logging the transaction to a transaction log buffer in response to detecting that the transaction matches one of the filter patterns.
Claims20
A method for communications within a semiconductor chip, the method comprising:
- storing filter patterns including an address range filter pattern;
- using an on-chip communications fabric to carry transactions from a first core circuit to a second core circuit;
- using a transaction filter located between the first core circuit and the on-chip communications fabric to monitor transactions carried by the on-chip communications fabric between the first core circuit and the second core circuit;
- executing, by the transaction filter, one of a set of actions in response to detecting a transaction that matches one of the filter patterns;
- and
- logging the transaction to a transaction log buffer in response to detecting that the transaction matches one of the filter patterns.
A semiconductor chip comprising:
- a first core circuit;
- a second core circuit;
- an on-chip communications fabric that carries transactions from the first core circuit to the second core circuit;
- and
- a transaction filter circuit located between the first core circuit and the on-chip communications fabric and communicatively coupled to the first core circuit and the on-chip communications fabric, wherein the transaction filter circuit is configured to:
- monitor transactions passing between the first core circuit and the second core circuit,
- execute one of a set of actions in response to detecting a transaction that matches one of a plurality of filter patterns, and
- log a transaction to a transaction log buffer in response to detecting that the transaction matches one of the filter patterns.
A semiconductor chip comprising:
- a first core circuit;
- a second core circuit;
- a communications means for carrying a transaction from the first core circuit to the second core circuit,
- a filtering means for determining that the transaction meets a criterion;
- a means for executing a means for reacting to the transaction meeting the criterion;
- and
- a means for blocking the transaction if and only if the means for reacting to the transaction meeting the criterion prevents passing the transaction,
- wherein the filtering means is located between the first core circuit and the communications means.
Dependencies are inferred from the claim text.