Multi-stage amplifier circuit

A multi-stage amplifier circuit, comprising:

• a pre-stage amplifier, which is configured to operably amplify a voltage difference between a first input terminal and a second input terminal of the pre-stage amplifier, so as to generate a plurality of pre-stage transconductance currents flowing through a plurality of corresponding pre-stage transconductance nodes, wherein the plurality of pre-stage transconductance currents include a first pre-stage transconductance current and a second pre-stage transconductance current which are in-phase with each other;
• and
• a floating control circuit, which is configured to operably generate an upper driving signal and a lower driving signal according to the first pre-stage transconductance current and the second pre-stage transconductance current, wherein the floating control circuit includes a first sub-floating control circuit and a second sub-floating control circuit which are coupled to each other, wherein the first sub-floating control circuit and the second sub-floating control circuit are configured to operably generate a first sub-floating control signal and a second sub-floating control signal, respectively;
• wherein the first sub-floating control signal and the second sub-floating control signal correspond to one and the other of the upper driving signal and the lower driving signal, respectively;
• wherein the first sub-floating control circuit includes:
• a first floating reference transistor, which is configured to operably receive the first pre-stage transconductance current and which is configured as a source follower;
• and
• a first floating amplifier, which is coupled to the first floating reference transistor to forma feedback control loop, wherein the first floating amplifier is configured to operably generate the first sub-floating control signal according to a floating reference level in the floating control circuit by feedback control;
• wherein the first sub-floating control signal is configured to operably control a gate of the first floating reference transistor, and wherein the floating reference level is generated according to the second pre-stage transconductance current;
• wherein the first sub-floating control signal and the second sub-floating control signal are floating with reference to voltages at the plurality of corresponding pre-stage transconductance nodes, and wherein there is a predetermined voltage difference between the first sub-floating control signal and the second sub-floating control signal, wherein the predetermined voltage difference is correlated with a gate-source voltage of the first floating reference transistor.