Loop height measurement of overlapping bond wires
AssigneeEmage Vision Pte. Ltd.
InventorsSoon Wei Wong, Victor Vertoprakhov
Life of this patent
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Abstract
An apparatus and method for measuring loop height of overlapping bonded wires, interconnecting the pads of a single or stacked silicon chips to the pads of a substrate taking the steps of: focussing of an optical assembly at multiple points of the bond wire including overlapping bond wires, capturing an image of the bond wire at each of the predetermined focused points; calculating the height of each point of the wire with respect to a reference plane; and tabulating the height data using the X, Y and Z coordinates.
Claims5
Apparatus for inspecting Z height and profile of bonded wires on multi stacked dies or like article, comprising:
- an imaging device mounted on a means capable of moving in the X, Y & Z axis coupled with high resolution encoders, to capture images of focussed points on bonding wires and their respective X, Y & Z positions, at different planes;
- the imaging device optically coupled with a lens having a pre-determined focal depth;
- a strobed illuminating means having a pre-determined angle to enable image capture of illuminated bonded wires to eliminate image noise of closely placed bonded wires;
- a second illumination means mounted on the pedestal to illuminate the object under inspection to enable capturing of a backlit image.
A method for measuring the Z height and profile of wires bonded between pads of a two or more stacked semiconductor chips and a substrate, said method comprising the steps of:
- moving an image capturing system in the X, Y & Z direction to focus said image capturing system onto pre-set multiple points on the bonded wires;
- capturing images of said multiple points on the desired bonding wires in multiple Z axis planes using strobed illumination;
- reading the encoders positions of every point on the set of bonding wires and tabulating their respective X Y & Z points;
- calculating the heights, and lateral displacement of all said tabulated points of the bonding wires around the entire stacked die semiconductor chip and linearly interpolating each point to their neighbouring point to form an angular profile of every bonding wire;
- plotting a 3D graph using the tabulated points.
- analysing the 3D graph to detect bonding wires in close proximity in the XY or Z position and comparing them with pre-set parameters for rejecting or accepting the bonded multi stacked die;
- communicating the results and analysed parameters to the external interface.
Dependencies are inferred from the claim text.