Circuit implementation in resource constrained systems
AssigneeRaytheon Company
InventorsHrishikesh Shinde, Daryl Coleman
Life of this patent
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Abstract
Methods and apparatus for implementing a bus in a resource constrained system. In embodiments, a first FPGA is to a parallel bus and a second FPGA is connected to the first FPGA via a serial interface but not the parallel bus. The first FPGA processes a transaction request, which has a parallel bus protocol format, to the second FPGA by an initiator and converts the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs. The first FPGA responds to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.
Claims20
A method, comprising:
- connecting a first FPGA to a parallel bus;
- connecting a second FPGA to the first FPGA via a serial interface, wherein the second FPGA is not connected to the parallel bus;
- processing, by the first FPGA, a transaction request to the second FPGA by an initiator, wherein the transaction request has a format in a protocol for the parallel bus;
- converting the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs;
- and
- responding, by the first FPGA, to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete
- wherein the initiator comprises a legacy application, and wherein the first and second FPGAs are partitioned from a legacy FPGA.
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A system, comprising:
- a first FPGA connected to a parallel bus;
- a second FPGA connected to the first FPGA via a serial interface, wherein the second FPGA is not connected to the parallel bus;
- wherein the first FPGA is configured to process a transaction request to the second FPGA by an initiator, wherein the transaction request has a format in a protocol for the parallel bus,
- wherein the first and second FPGAs are configured to convert the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs, and
- wherein the first FPGA is further configured to respond to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete.
A system, comprising:
- a first FPGA connected to a parallel bus;
- a second FPGA connected to the first FPGA via a serial interface, wherein the second FPGA is not connected to the parallel bus;
- wherein the first FPGA is configured to process a transaction request to the second FPGA by an initiator, wherein the transaction request has a format in a protocol for the parallel bus,
- wherein the first and second FPGAs are configured to convert the transaction request to the second FPGA into a transaction on the serial interface between the first and second FPGAs, and
- wherein the first FPGA is further configured to respond to the initiator via the parallel bus indicating that the transaction request in the format for the parallel bus to the second FPGA is complete,
- wherein the initiator comprises a legacy application, and
- wherein the first and second FPGAs are partitioned from a legacy FPGA.
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Dependencies are inferred from the claim text.