Processor that mitigates side channel attacks by providing random load data as a result of execution of a load operation that does not have permission to access a load address
AssigneeVentana Micro Systems Inc.
InventorsJohn G. Favor, Srivatsan Srinivasan
Life of this patent
Estimating the term…
Abstract
A microprocessor that mitigates side channel attacks. The microprocessor includes a data cache memory and a load unit that receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The load unit detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist and provides random load data as a result of the execution of the load operation.
Claims29
A microprocessor for mitigating side channel attacks, comprising:
- a data cache memory;
- a load unit configured to receive a load operation that specifies a load address;
- wherein the processor is configured to perform speculative execution of instructions;
- wherein the processor is configured to execute instructions out of program order;
- and
- wherein the load unit is configured to:
- detect that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist;
- and
- provide random load data as a result of the execution of the load operation.
A method for mitigating side channel attacks, comprising:
- in a microprocessor configured to perform speculative execution of instructions and to execute instructions out of program order:
- issuing a load operation to a load unit of the microprocessor for execution, wherein the load operation specifies a load address;
- detecting, by the load unit, that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist;
- and
- providing, by the load unit, random load data as a result of the execution of the load operation.
A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor for mitigating side channel attacks, the microprocessor configured to speculatively execute instructions out of program order, wherein the microprocessor is configured by the instructions to perform operations comprising:
- issuing a load operation to a load unit of the microprocessor for execution, wherein the load operation specifies a load address;
- detecting, by the load unit, that the load operation does not have permission to access the load address;
- and
- providing, by the load unit, random load data as a result of the execution of the load operation.
Dependencies are inferred from the claim text.