Method and apparatus for high speed clock distribution

A method of clock distribution comprising:

• receiving a first voltage signal;
• converting the first voltage signal into a first current signal using a voltage-to-current driver;
• transmitting the first current signal into a second current signal using a transmission line;
• relaying the second current signal into a third current signal using a current buffer;
• converting the third current signal into a second voltage signal using a LC (inductor-capacitor) tank as a load;
• transmitting the second voltage signal into a third voltage signal using a first CDW (capacitively driven wire);
• amplifying the third voltage signal into a fourth voltage signal using a first inverter buffer;
• transmitting the second voltage signal into a fifth voltage signal using a second CDW;
• and
• amplifying the fifth voltage signal into a sixth voltage signal using a second inverter buffer.

A method of clock distribution comprising:

• receiving a remote voltage signal;
• transmitting the remote voltage signal into a local voltage signal using a current-mode transmission scheme that comprises a cascade of a voltage-to-current driver, a transmission line, a current buffer, and a LC (inductor-capacitor) tank;
• transmitting the local voltage signal into a first destination voltage signal using a voltage-mode transmission scheme that comprises a cascade of a first capacitively driven wire and a first inverter buffer;
• and
• transmitting the local voltage signal into a second destination voltage signal using a voltage-mode transmission scheme that comprises a cascade of a second capacitively driven wire and a second inverter buffer.