Phase interpolation circuit with high linearity

A phase interpolation circuit with a high linearity, comprising:

• a first parallel circuit constituted by M phase interpolation units, and
• a second parallel circuit constituted by N phase interpolation units;
• wherein an input terminal of the first parallel circuit is connected to a first clock input terminal and the input terminal of the first parallel circuit is grounded via a first capacitor;
• an output terminal of the first parallel circuit is connected to a clock output terminal;
• an input terminal of the second parallel circuit is connected to a second clock input terminal and the input terminal of the second parallel circuit is grounded via a second capacitor;
• an output terminal of the second parallel circuit is connected to the clock output terminal;
• the clock output terminal is grounded via a zeroth capacitor;
• the clock output terminal outputs a plurality of output clock signals with different phases by controlling an on-off state of a branch, wherein each phase interpolation unit in the first parallel circuit and the second parallel circuit is located at the branch;
• and
• a circuit parameter of each phase interpolation unit corresponds to a target output weight respectively, and the target output weight of each phase interpolation unit is determined by iteration to minimize an output delay difference of the phase interpolation circuit, wherein the output delay difference indicates a phase difference between the plurality of output clock signals with different phases outputted by the phase interpolation circuit through the clock output terminal.