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US 2022/0103181 A1Published application
Phase lock loop reference loss detection
AssigneeTexas Instruments Incorporated
InventorsShailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das
Life of this patent
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Abstract
In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.
Claims16
A circuit, comprising:
- a first input configured to receive a first clock signal;
- a second input configured to receive a second clock signal;
- a comparator coupled to the first input and the second input, the comparator configured to perform a comparison of the first clock signal and the second clock signal;
- and
- an output configured to output a fault signal based on the comparison.
2 more elements
A method, comprising:
- receiving a first clock signal;
- receiving a second clock signal;
- determining a comparison of the first clock signal and the second clock signal;
- and
- outputting a fault signal based on the comparison.
2 more elements
Dependencies are inferred from the claim text.