Subthreshold ratioed logic circuit and chip

A chip, comprises a subthreshold ratioed logic circuit, wherein, the subthreshold ratioed logic circuit comprising a pull-up module, a voltage regulation module, a pull-up PMOS transistor, and a pull-down module corresponding to the pull-up module that is turned on or off;

• the first end of the pull-up module is connected with an external circuit that provides an input signal, the second end of the pull-up module is connected with the source of the pull-up PMOS transistor and a power supply VDD, and the third end of the pull-up module is connected with the second end of the voltage regulation module;
• the first end of the voltage regulation module is connected with a compensation adjustment circuit that provides a compensation signal, the third end of the voltage regulation module is grounded, and the connection node of the second end of the voltage regulation module and the third end of the pull-up module is also connected with the gate of the pull-up PMOS transistor;
• the drain of the pull-up PMOS transistor is connected with the output of the subthreshold ratioed logic circuit, and the drain of the pull-up PMOS transistor is also connected with the second end of the pull-down module, and the first end of the pull-down module is connected with the external circuit, the third end of the pull-down module is grounded;
• the pull-up module and the pull-down module are turned on or off according to the input signal, and control the pull-up current of the pull-up PMOS transistor in combined with the voltage regulation module, so that the output of the subthreshold ratioed logic circuit can quickly output a level signal;
• wherein, the pull-up module, the pull-down module, and the voltage regulation module are all sub-threshold conduction states when turned on.