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US 2022/0103176 A1Published application
Buffer circuit, receiver circuit including the buffer circuit, and semiconductor apparatus including the receiver circuit
AssigneeSK hynix Inc.
InventorsJin Ha HWANG, Yo Han JEONG, Eun Ji CHOI
Life of this patent
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Abstract
The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.
Claims7
A buffer circuit comprising:
- a first logic gate configured to generate an output according to a data;
- and
- a second logic gate coupled to an internal voltage terminal and configured to receive the output of the first logic gate to output a buffer signal according to a first enable signal, and configured to compensate for a duty skew of the buffer signal according to a level of an external voltage.
A receiver circuit comprising:
- a first buffer circuit coupled to an internal voltage terminal and configured to receive data and output the data as a first buffer signal according to a first enable signal and to compensate for a duty skew of the first buffer signal according to an external voltage;
- and
- a second buffer circuit configured to receive the data and output the data as a second buffer signal in response to a reference voltage according to a second enable signal.
Dependencies are inferred from the claim text.