Level converting enable latch

A level converting enable latch, comprising:

• a level shifter circuit, arranged to receive a first data input signal, and generate and output a first data output signal, wherein a voltage swing of the first data output signal is different from a voltage swing of the first data input signal;
• and
• a latch circuit, arranged to receive the first data output signal and set a second data output signal in response to the first data output signal when a latch enable signal is set by a first logic value, and latch the second data output signal when the latch enable signal is set by a second logic value that is different from the first logic value;
• wherein the level shifter circuit comprises:
• a first transistor, having a control terminal arranged to receive the first data input signal;
• a second transistor, having a control terminal arranged to receive a second data input signal that is an inverse of the first data input signal;
• a first footer transistor, having a first connection terminal coupled to a first connection terminal of the first transistor and a second connection terminal coupled to a reference voltage, wherein the first footer transistor is turned on when the latch enable signal is set by the first logic value, and is turned off when the latch enable signal is set by the second logic value;
• and
• a second footer transistor, having a first connection terminal coupled to a first connection terminal of the second transistor and a second connection terminal coupled to the reference voltage, wherein the second footer transistor is turned on when the latch enable signal is set by the first logic value, and is turned off when the latch enable signal is set by the second logic value;
• wherein the first data output signal is output at a second connection terminal of the second transistor.

A level converting enable latch, comprising:

• a level shifter circuit, arranged to receive a first data input signal, and generate and output a first data output signal, wherein a voltage swing of the first data output signal is different from a voltage swing of the first data input signal;
• and
• a latch circuit, arranged to receive the first data output signal and set a second data output signal in response to the first data output signal when a latch enable signal is set by a first logic value, and latch the second data output signal when the latch enable signal is set by a second logic value that is different from the first logic value;
• wherein the level shifter circuit comprises:
• a first transistor, having a control terminal arranged to receive the first data input signal;
• a second transistor, having a control terminal coupled to the control terminal of the first transistor, and a first connection terminal coupled to a connection terminal of the first transistor;
• a third transistor, having a connection terminal arranged to output the first data output signal;
• a fourth transistor, having a control terminal coupled to a control terminal of the third transistor, and a first connection terminal coupled to the connection terminal of the third transistor;
• a fifth transistor, having a control terminal coupled to the connection terminal of the third transistor, a first connection terminal coupled to a second connection terminal of the second transistor, and a second connection terminal coupled to a reference voltage;
• a sixth transistor, having a control terminal coupled to the connection terminal of the first transistor, a first connection terminal coupled to a second connection terminal of the fourth transistor, and a second connection terminal coupled to the reference voltage;
• and
• a seventh transistor, having a first connection terminal coupled to the second connection terminal of the fourth transistor, and a second connection terminal coupled to the reference voltage, wherein the seventh transistor is turned off when the latch enable signal is set by the first logic value, and is turned on when the latch enable signal is set by the second logic value;
• the latch circuit comprises:
• a multiplexer, having a first input node arranged to receive an internal signal of the latch circuit, a second input node arranged to receive a second data input signal that is an inverse of the first data input signal, and an output node arranged to output a multiplexer output signal to both of the control terminal of the third transistor and the control terminal of the fourth transistor, wherein the multiplexer selects the internal signal as the multiplexer output signal when the latch enable signal is set by the second logic value, and selects the second data input signal as the multiplexer output signal when the latch enable signal is set by the first logic value.