Multi-gated i/o system, semiconductor device including and method for generating gating signals for same

A generator to generate a power-on (PO) signal (PO signal generator), the PO signal generator comprising:

• a supply-variation sensitivity-reducing (SVSR) device coupled between a first reference voltage and a first node, the SVSR device including a first switch and a first load coupled serially;
• a second switch coupled between the first node and a second reference voltage;
• and
• a buffer having an input coupled to the first node and an output configured to provide a PO signal.

A generator to generate a power-on (PO) signal (PO signal generator), the PO signal generator comprising:

• a supply-variation sensitivity-reducing (SVSR) device coupled between a first reference voltage and a first node, the SVSR device including:
• a first switch and a first load coupled in series between the first node and a second node;
• and
• a second resistor coupled and a second switch coupled in parallel between the second node and a first reference voltage;
• each of the first and second switches including a corresponding control input;
• a third switch coupled between the first node and a second reference voltage, the third switch including a control input;
• the control inputs of each of the first switch and the third switch being coupled to a monitored voltage;
• and
• a buffer having an input coupled to the first node and an output configured to provide a PO signal, the control input of the second switch being coupled to a third node, the third node being internal to the buffer;
• and
• wherein a voltage on the third node represents a threshold voltage of the generator;
• and
• the threshold voltage of the generator;
• exhibits hysteresis with respect to the monitored voltage.