Active N-Well Switching Circuit for Power Switches

A voltage switching circuit, comprising:

• a comparator connected to compare first and second power supplies and to generate a first selection signal identifying which of the first and second power supplies is higher;
• at least a first level shifter connected to receive the first selection signal and to generate a first level-shifted gate control signal;
• and
• first and second cross-coupled PMOS transistors connected to receive the first level-shifted gate control signal from the first level shifter, each cross-coupled PMOS transistor comprising:
• a gate connected to a drain of the other cross-coupled PMOS transistor,
• a drain tied to a gate of the other cross-coupled PMOS transistor, and
• a source connected to an output voltage node that is also coupled to an n-well for the cross-coupled PMOS transistor;
• wherein the first level-shifted gate control signal is connected to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.

A method, comprising:

• receiving first and second independent power supply voltages;
• remapping the first and second independent power supply voltages into first and second gate driving signals, where the first gate driving signal is connected to the first or second independent power supply voltage that is higher and where the second gate driving signal is connected to ground;
• and
• supplying the first and second gate driving signals, respectively, to gates of first and second cross-coupled PMOS transistors having an output voltage node connected in common to the sources and n-wells of the first and second cross-coupled PMOS transistors, thereby pulling a first gate of one of the cross-coupled PMOS transistors to ground so that the higher of the first and second independent power supply voltages is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum output supply voltage at the output voltage node.