Clock duty cycle correction
AssigneeApple Inc.
InventorsSuresh Balasubramanian, Sunil Bhosekar, Bruce Andrew Doyle, Chad O. Lackey, Sharath R. Srinivasan, Erick O. Torres, Khaled M. Alashmouny
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AssigneeApple Inc.
InventorsSuresh Balasubramanian, Sunil Bhosekar, Bruce Andrew Doyle, Chad O. Lackey, Sharath R. Srinivasan, Erick O. Torres, Khaled M. Alashmouny
Estimating the term…
Systems, methods, and devices are provided for calibrating and correcting a clock duty cycle. An integrated circuit may include a clock tree that provides a clock signal and a circuit that is sensitive to clock duty cycle that receives the clock signal at a lower level of the clock tree. A first duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a first target duty cycle at a higher level of the clock tree. A second duty cycle correction circuit may adjust a clock duty cycle of the clock signal to a second target duty cycle at the lower level of the clock tree.
An integrated circuit comprising:
A method comprising:
A method comprising:
Dependencies are inferred from the claim text.