Level shifter circuits
AssigneeSamsung Electronics Co., Ltd.
InventorsAnkur GUPTA, Lava Kumar PULLURU, Parvinder Kumar RANA
Life of this patent
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Abstract
An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the A output of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.
Claims20
An apparatus comprising:
- an NMOS transistor having a drain;
- a first PMOS transistor having a drain connected to the drain of the NMOS transistor;
- a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor;
- a first digital logic circuit having a drain and a gate;
- a first inverter having an input connected to the output of the level shifter and the drain of the first digital logic circuit;
- and
- a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.
A apparatus comprising:
- an NMOS transistor having a drain;
- a first PMOS transistor having a drain connected to the drain of the NMOS transistor;
- a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor;
- a first inverter having an input connected to the output of the level shifter;
- and
- a parallel path enabled only during a falling edge of the input of the level shifter.
A memory device, comprising:
- a bit cell array including a plurality of bit cells;
- a sense amplifier configured to read data corresponding to a first power domain from the bit cell array;
- and
- a level shifter circuit configured to convert the read data from the first power domain to a second power domain,
- wherein, the level shifter circuit includes:
- an NMOS transistor having a drain,
- a first PMOS transistor having a drain connected to the drain of the NMOS transistor,
- a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor,
- a first digital logic circuit having a drain and a gate,
- a first inverter having an input connected to the output of the level shifter and the drain of the first digital logic circuit, and
- a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the memory device during a read operation.
Dependencies are inferred from the claim text.