Concept for a buffered flipped voltage follower and for a low dropout voltage regulator

Abstract

Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (Mp) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (Mc) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (−gmf) comprising an input terminal and an output terminal. The first terminal of the first transistor (Mp) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (Mp) is coupled with the first terminal of the second transistor (Mc) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−gmf). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−gmf).

Dependencies are inferred from the claim text.