Impedance control in merged stacked fet amplifiers

An amplifier circuit, comprising:

• a plurality of stacked field-effect (FET) transistors (M1, . . . , Mn) comprising an input transistor (M1) and one or more cascode transistors (M2, . . . , Mn), the one or more cascode transistors comprising an output transistor (Mn);
• and
• one or more compensation networks (Zg2, . . . , Zgn), each connected between a gate (G2, . . . , Gn) of a respective cascode transistor of the one or more cascode transistors and a reference ground;
• wherein each compensation network comprises:
• a series-connected resistive-capacitive network (Zgn1) comprising a first resistor (Rsk) in series connection with a capacitor (Ck);
• and
• a parallel-connected resistive-inductive network (Zgn2) comprising a second resistor (Rpk) connected in parallel with an inductor (Lk),
• wherein
• a first terminal of the series-connected resistive-capacitive network (Zgn1) is connected to the gate of the respective cascode transistor, a second terminal of the series-connected resistive-capacitive network (Zgn1) is connected to a first terminal of the parallel-connected resistive-inductive network (Zgn2), and a second terminal of the parallel-connected resistive-inductive network (Zgn2) is connected to the reference ground.