Drive circuit for power converter

A drive circuit for a power converter that includes an upper-arm switch and a lower-arm switch, each of which has first and second terminals, diodes being connected in antiparallel to the respective upper- and lower-arm switches, the drive circuit comprising:

• a signal generator configured to generate a gate signal that alternately turns on the upper- and lower-arm switches while preventing the upper- and lower-arm switches being simultaneously in an on state;
• a voltage divider configured to divide:
• a first voltage at the first terminal of at least one target switch that is at least one of the upper- and lower-arm switches;
• and
• a second voltage at the second terminal of the at least one target switch to thereby obtain a first divided terminal voltage and a second divided terminal voltage;
• and
• a differential circuit unit having a first input terminal and a second input terminal, the first divided terminal voltage being inputted to the first input terminal of the differential circuit unit, the second divided terminal voltage being inputted to the second input terminal of the differential circuit unit, the differential circuit unit being configured to generate an output voltage based on a difference between the first and second divided terminal voltages,
• the differential circuit unit being configured such that:
• resetting of the output voltage of the differential circuit unit is carried out;
• and
• the resetting of the output voltage of the differential circuit unit is cancelled, a value of the difference between the first and second divided terminal voltages at a timing of cancelling the resetting being defined as a reference voltage,
• the differential circuit unit being configured to generate, as the output voltage, a product of a voltage change from the reference voltage and a predetermined amplification factor after cancelling of the resetting of the differential circuit unit,
• the signal generator being configured to generate the gate signal for each of the upper- and lower-arm switches in accordance with a value of the output voltage of the differential circuit unit while the upper- and lower-arm switches are in an off state.