Triple-gate mos transistor and method for manufacturing such a transistor

A triple-gate MOS transistor, comprising:

• a semiconductor substrate;
• trenches in the semiconductor substrate on either side of an area of an active region;
• an electrically isolating layer on an internal surface of each of said trenches;
• a semiconductive or electrically conductive material filling the trenches up to an upper surface of the active region so as to form respective vertical gates on opposite sides of a channel;
• a further electrically isolating layer on the upper surface of the active region at the channel;
• and
• a semiconductive or electrically conductive material on the further electrically isolating layer so as to form a horizontal gate.

A circuit, comprising:

• a non-volatile memory cell including a vertical gate transistor;
• and
• a triple-gate MOS transistor;
• wherein the vertical gate transistor of the non-volatile memory cell includes a first trench extending into a semiconductor substrate;
• wherein the triple-gate MOS transistor includes second trenches in the semiconductor substrate on either side of an area of an active region;
• an electrically isolating layer on an internal surface of each of said first and second trenches;
• a first semiconductive or electrically conductive material filling the first and second trenches, said first semiconductive or electrically conductive material forming a first vertical gate of the vertical gate transistor and respective second vertical gates on opposite sides of a channel of the triple-gate MOS transistor;
• a further electrically isolating layer on the upper surface of the active region at the channel;
• and
• a semiconductive or electrically conductive material on the further electrically isolating layer so as to form a horizontal gate of the triple-gate MOS transistor.