Gate and fin trim isolation for advanced integrated circuit structure fabrication

A method of fabricating an integrated circuit structure, the method comprising:

• forming a plurality of fins;
• forming a fin trim isolation structure in one of the plurality of fins;
• subsequent to forming the fin trim isolation structure, forming a gate structure over the plurality of fins;
• and
• subsequent to forming the gate structure, forming epitaxial source or drain structures in or on the plurality of fins.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure fabricated according to a method comprising:
• forming a plurality of fins along a first direction;
• removing a portion of one of the plurality of fins to form a trench;
• forming an isolation structure in the trench, the isolation structure extending above the one of the plurality of fins;
• forming a gate structure over the plurality of fins, the gate structure along a second direction orthogonal to the first direction;
• forming a dielectric spacer along sidewalls of the gate structure and the isolation structure;
• and
• subsequent to forming the dielectric spacer, forming epitaxial source or drain structures in or on the plurality of fins.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure fabricated according to a method comprising:
• forming a plurality of fins;
• forming a fin trim isolation structure in one of the plurality of fins;
• subsequent to forming the fin trim isolation structure, forming a gate structure over the plurality of fins;
• and
• subsequent to forming the gate structure, forming epitaxial source or drain structures in or on the plurality of fins.