Damage implantation of cap layer
AssigneeTexas Instruments Incorporated
InventorsMahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta
Life of this patent
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Abstract
A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
Claims17
A method for fabricating an integrated circuit, comprising:
- performing a source/drain implant of a semiconductor wafer, the semiconductor wafer including a partial transistor containing a gate stack, source/drain extension regions, and source/drain sidewalls;
- forming a cap layer over the semiconductor wafer having the source/drain implant and the source/drain sidewalls, the cap layer comprising silicon and carbon;
- performing a source/drain anneal of the semiconductor wafer, wherein the source/drain anneal densifies and reduces a thickness of the cap layer, and
- performing a damage implant of the cap layer.
A method for fabricating a transistor on a semiconductor wafer, comprising:
- performing a source/drain implant of the semiconductor wafer, the semiconductor wafer including a partial transistor containing a gate stack, source/drain extension regions, and source/drain sidewalls;
- forming a cap layer over the semiconductor wafer having the source/drain implant and the source/drain sidewalls, the cap layer comprising silicon and carbon;
- performing a damage implant of the cap layer;
- and
- performing a source/drain anneal following the damage implant.
A method for fabricating an integrated circuit, comprising:
- performing a source/drain implant of a semiconductor wafer, the semiconductor wafer including a partial transistor containing a gate stack, source/drain extension regions, and source/drain sidewalls;
- forming a cap layer over the semiconductor wafer having the source/drain implant and the source/drain sidewalls, the cap layer comprising silicon and carbon;
- performing a source/drain anneal of the semiconductor wafer, wherein the source/drain anneal densifies and reduces a thickness of the cap layer;
- and
- performing a damage implant of the cap layer, wherein performing the damage implant of the cap layer comprises implanting Ar into the cap layer.
Dependencies are inferred from the claim text.