Bipolar junction device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsZi-Ang Su, Ming-Shuan Li, Chih Chieh Yeh
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Abstract
The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.
Claims22
A bipolar junction transistor (BJT), comprising:
- a first epitaxial feature disposed over a well region;
- a second epitaxial feature disposed over the well region;
- a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature;
- a gate structure wrapping around each of the vertical stack of channel members;
- a first electrode coupled to the well region;
- an emitter electrode disposed over and coupled to the first epitaxial feature;
- and
- a second electrode disposed over and coupled to the second epitaxial feature.
4-5. (canceled)
10-20. (canceled)
A semiconductor structure, comprising:
- a first epitaxial feature and a second epitaxial feature disposed over a well region of a semiconductor body;
- a silicide layer disposed below and in contact with the semiconductor body;
- a vertical stack of nanostructures each extending lengthwise between the first epitaxial feature and the second epitaxial feature;
- and
- a gate structure wrapping around each of the vertical stack of nanostructures,
- wherein the gate structure is electrically floating.
A semiconductor structure, comprising:
- a first epitaxial feature and a second epitaxial feature disposed over a well region of a semiconductor body;
- a plurality of nanostructures each extending lengthwise between the first epitaxial feature and the second epitaxial feature;
- a gate structure wrapping around each of the plurality of nanostructures;
- a first electrode coupled to the well region;
- an emitter electrode disposed over and coupled to the first epitaxial feature;
- and
- a second electrode disposed over and coupled to the second epitaxial feature,
- wherein the gate structure is electrically floating.
Dependencies are inferred from the claim text.