Method of Forming Backside Power Rails
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPei-Wei Wang, Chih-Chuan Yang, Yu-Kuan Lin, Choh Fei Yeap
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Abstract
A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.
Claims20
A method, comprising:
- forming a composite substrate that includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer;
- forming a fin structure from the fourth semiconductor layer;
- forming a dummy gate stack over a channel region of the fin structure;
- recessing a source region and a drain region of the fin structure to form a source opening and a drain opening, the channel region being disposed between the source region and the drain region;
- selectively etching the source region of the fin structure to extend the source opening through the third semiconductor layer to form an extended source opening;
- selectively forming a semiconductor plug into the extended source opening;
- planarizing the composite substrate to remove the substrate, the first semiconductor layer, and the second semiconductor layer to expose the semiconductor plug;
- after the planarizing, replacing the third semiconductor layer with a dielectric layer;
- and
- replacing the semiconductor plug with a backside source contact.
A method, comprising:
- forming a composite substrate that includes a substrate, a first silicon germanium (SiG) layer over the substrate, a first silicon (Si) layer over the first SiGe layer, a second SiGe layer over the first Si layer, and a second Si layer over the second SiGe layer;
- forming a fin structure from the second Si layer;
- forming a dummy gate stack over a channel region of the fin structure;
- recessing a source region and a drain region of the fin structure to form a source opening and a drain opening, the channel region being disposed between the source region and the drain region;
- selectively etching the source region of the fin structure to extend the source opening through the second SiGe layer to form an extended source opening;
- selectively forming a Si plug into the extended source opening;
- after the selective forming of the Si plug, forming a source feature over the Si plug and a drain feature in the drain opening;
- planarizing the composite substrate to remove the substrate, the first SiGe layer, and the first Si layer to expose the Si plug;
- after the planarizing, replacing the second SiGe layer with a dielectric layer;
- and
- replacing the Si plug with a backside source contact.
A semiconductor structure, comprising:
- a source feature and a drain feature;
- a channel structure disposed between the source feature and the drain feature;
- a dielectric layer disposed over the drain feature;
- a backside source contact over the source feature and extending through the dielectric layer;
- and
- a backside power rail disposed over the dielectric layer and in contact with the backside source contact.
Dependencies are inferred from the claim text.