Method of making a plurality of high density logic elements with advanced cmos device layout

A semiconductor apparatus, comprising:

• a substrate having first implanted regions of P+ or N+ dopants;
• a layer stack on the substrate, the layer stack having a metal layer of a first metal positioned between a first dielectric layer and a second dielectric layer;
• a plurality of vertical channels in the layer stack, each vertical channel located over one of the implanted regions, wherein sides of the vertical channels are covered by a high-K material;
• a P+ epitaxial material or an N+ epitaxial material filling each vertical channel over the P+ or N+ dopants respectively;
• sidewall structures surrounding each vertical channel;
• a first layer of salicide covering the substrate between the sidewall structures;
• a second layer of salicide covering each vertical channel;
• and
• metal wiring connected to the first metal, the first layer of salicide and the second layer of salicide, the metal wiring formed within via channels of a dielectric film covering the substrate.

A semiconductor apparatus, comprising:

• a substrate having first implanted regions of P+ dopants alternating with second implanted regions of N+ dopants;
• a diffusion break located in the substrate between the regions of P+ dopants and the regions N+ dopants;
• a layer stack on the substrate, the layer stack having a metal layer of a first metal positioned between a first dielectric layer and a second dielectric layer;
• P+ epitaxially grown vertical channels in the layer stack located over the P+ dopants;
• N+ epitaxially grown vertical channels in the layer stack located over the N+ dopants;
• a high-K material on sidewalls of each vertical channel;
• sidewall structures surrounding each vertical channel, wherein the sidewall structure surrounding a P+ vertical channel includes the first metal and the sidewall structure surrounding an N+ vertical channel has the first metal replaced by a second metal;
• a first layer of salicide covering the substrate between the sidewall structures;
• a second layer of salicide covering each vertical channel;
• and
• metal wiring connected to the first metal, the first layer of salicide and the second layer of salicide, the metal wiring formed within via channels of a dielectric film covering the substrate.