Semiconductor device

A semiconductor device comprising:

• a substrate including an element isolation layer and an active region defined by the element isolation layer and arranged in a first direction;
• a plurality of buried contacts connected to the active region and arranged in a second direction different from the first direction;
• a plurality of bit line structures between the plurality of buried contacts that are adjacent to each other, the plurality of bit line structures extending across the active region in a third direction crossing the second direction;
• and
• a spacer structure extending in the third direction along side surfaces of the plurality of bit line structures,
• wherein each of the plurality of bit line structures includes a first bit line structure overlapping the active region and a second bit line structure overlapping the element isolation layer,
• each of the buried contacts includes a first portion recessed into the element isolation layer and the active region between the first bit line structure and the second bit line structure, and a second portion on the first portion, the second portion having a pillar shape with a width less than a width of a top surface of the first portion,
• a width of the first portion decreases away from a top surface of the substrate, and
• the spacer structure includes a first spacer including silicon oxide and disposed at an outermost side, the first spacer extending along a side surface of the second portion, and a second spacer including silicon nitride and extending along the first spacer on the first spacer.

A semiconductor device comprising:

• a substrate having a gate trench;
• a gate electrode filling a part of the gate trench and extending in a first direction;
• a source/drain region on a side surface of the gate electrode;
• a plurality of buried contacts including a buried contact electrically connected to the source/drain region, the plurality of buried contacts being arranged in the first direction;
• a landing pad on the buried contact;
• a capacitor structure on the landing pad and electrically connected to the landing pad and the buried contact;
• a bit line structure extending in a second direction crossing the first direction between the plurality of buried contacts spaced apart in the first direction, the bit line structure including a conductive pattern and a capping pattern on the conductive pattern;
• and
• a spacer structure on a side surface of the bit line structure and extending in the second direction,
• wherein in cross-sectional view taken along the first direction, the buried contact includes a first portion recessed into the substrate and having an elliptical hemispherical shape convex toward the substrate, and a second portion having a pillar shape having a width smaller than a width of a top surface of the first portion, the buried contact spaced apart from the bit line structure by the spacer structure,
• the spacer structure includes a first spacer in contact with the second portion of the buried contact, a second spacer extending along a side surface of the first spacer on the first spacer, and a third spacer extending along a side surface of the second spacer on the second spacer,
• a boundary between the first portion of the buried contact and the second portion of the buried contact is positioned on a bottom surface of the first spacer, and
• the first spacer includes silicon oxide, the second spacer includes silicon nitride, and the third spacer includes at least one of air or silicon oxide.