Chip and method for self-aligned etching of contacts of chips

Abstract

The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a chip and a method for self-aligned etching of contacts of the chip. The chip includes a substrate layer, a salicide block layer and a dielectric layer; the salicide block layer covers the device layer; the salicide block layer comprises a first block layer and a second block layer sequentially stacked from the device layer; an etching selection ratio of the second block layer to the first block layer is high; The method includes: defining a contact pattern; performing first etching to remove the dielectric layer and the second block layer located at the position of the contact pattern, making a stop surface of the first etching be located in the first block layer; performing second etching to remove the first block layer located at the position of the contact pattern.

Dependencies are inferred from the claim text.