Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures

A method of fabricating an integrated circuit structure, the method comprising:

• forming a semiconductor structure above a substrate;
• forming a gate electrode over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure;
• forming a first semiconductor source or drain structure at a first end of the channel region at a first side of the gate electrode;
• forming a second semiconductor source or drain structure at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end;
• and
• forming a source or drain contact on the first or second semiconductor source or drain structure, the source or drain contact comprising an alloyed metal barrier layer and an inner conductive structure.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a semiconductor structure above a substrate;
• a gate electrode over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure;
• a first semiconductor source or drain structure at a first end of the channel region at a first side of the gate electrode;
• a second semiconductor source or drain structure at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end;
• and
• a source or drain contact on the first or second semiconductor source or drain structure, the source or drain contact comprising an alloyed metal barrier layer and an inner conductive structure.