# US 2022/0102518 A1 · Thicker corner of a gate dielectric structure around a recessed gate electrode for an mv device

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- Number: US 2022/0102518 A1
- Document ID: US20220102518A1
- Status: Published application
- Kind: A1
- Application number: 17/098,867
- Filed: 2020-11-16
- Published: 2022-03-31
- Earliest claimed: 2020-09-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Huan Chen; Kong-Beng Thei; Chien-Chih Chou; Alexander Kalnitsky; Szu-Hsien Liu; Huan-Chih Yuan
- Web page: https://patentgrep.com/patent/US20220102518A1

## CPC

- H10D 64/516: {the thicknesses being non-uniform}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/658: {having trench gate electrodes}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/01: Manufacture or treatment
- H10D 64/027: {by etching at gate locations}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

## Claims

### Claim 1

A semiconductor device comprising:
a well region within a substrate;
a source region and a drain region arranged within the substrate on opposite sides of the well region;
a gate electrode arranged over the well region, comprising a bottom surface arranged below a topmost surface of the substrate, and extending between the source region and the drain region;
a trench isolation structure surrounding the source region, the drain region, and the gate electrode; and
a gate dielectric structure separating the gate electrode from the well region, the source region, the drain region, and the trench isolation structure,
wherein the gate dielectric structure comprises a central portion having a first thickness and a corner portion having a second thickness, and wherein the second thickness is greater than the first thickness.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the gate electrode extends from the source region to the drain region in a first direction, wherein the gate electrode extends from a first side of the trench isolation structure to a second side of the trench isolation structure in a second direction perpendicular to the first direction, and wherein the corner portion of the gate dielectric structure is arranged directly over and contacts the first and second sides of the trench isolation structure.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the second thickness is at least three times greater than the first thickness.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first thickness of the central portion of the gate dielectric structure is measured between an bottommost surface and a first middle surface of the gate dielectric structure, wherein the second thickness of the corner portion of the gate dielectric structure is measured between the bottommost surface and a second middle surface of the gate dielectric structure, wherein the first middle surface is between the second middle surface and the bottommost surface of the gate dielectric structure, and wherein the second middle surface is below a topmost surface of the gate dielectric structure.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the corner portion of the gate dielectric structure has a third thickness measured in the same direction as the first and second thicknesses, and wherein the third thickness is greater than the first and second thicknesses.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the gate electrode extends from the source region to the drain region in a first direction, and wherein any line that extends through the source and drain region in the first direction does not extend through the corner portion of the gate dielectric structure.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a lower portion of the gate electrode arranged over the central portion of the gate dielectric structure is narrower than an upper portion of the gate electrode arranged over the corner portion of the gate dielectric structure.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the corner portion of the gate dielectric structure comprises a first region that directly overlies the isolation structure and a second region that directly overlies and contacts the well region, wherein the first region is thinner than the second region.

### Claim 9

A semiconductor device comprising:
a well region within a substrate;
a source region and a drain region arranged within the substrate on opposite sides of the well region;
a gate electrode arranged within the substrate and directly between the source region and the drain region;
a trench isolation structure continuously surrounding the source region, the drain region, and the gate electrode; and
a gate dielectric structure arranged on outer sidewalls and bottom surfaces of the gate electrode,
wherein the gate dielectric structure comprises a central portion having a first thickness, an inner corner portion having a second thickness that is greater than the first thickness, and an outer corner portion that has a third thickness greater than the second thickness, and
wherein the first, second, and third thicknesses are measured in a same direction from a bottommost surface of the gate dielectric structure.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the inner corner portion couples the central portion to the outer corner portion, wherein the outer corner portion overlies the trench isolation structure and the central portion extends between opposite sides of the trench isolation structure.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the inner corner portion of the gate dielectric structure overlies and directly contacts the trench isolation structure and the well region.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the gate electrode comprises an upper portion having a first width and a lower portion having a second width less than the first width, wherein an outer sidewall of the upper portion contacts the outer corner portion of the gate dielectric structure, and wherein an outer sidewall of the lower portion contacts the inner corner portion of the gate dielectric structure.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the gate dielectric structure comprises three dielectric layers.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the inner and outer corner portions of the gate dielectric structure comprise the three dielectric layers, and wherein the central portion of the gate dielectric structure comprises one of the three dielectric layers.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the one of the three dielectric layers is a topmost layer of the inner corner portion of the gate dielectric structure.

### Claim 16

A method comprising:
forming a trench isolation structure around a well region of a substrate;
removing a portion of the substrate to form a recess in the substrate, wherein outer sidewalls of the recess are defined by the trench isolation structure;
forming a first gate dielectric layer over surfaces of the recess in the substrate;
forming a second gate dielectric layer over the first gate dielectric layer;
performing a removal process to remove central portions of the first and second gate dielectric layers, wherein after the removal process, portions of the first and second gate dielectric layers remain on the trench isolation structure;
forming a third gate dielectric layer over surfaces of the recess in the substrate and over the second gate dielectric layer; and
forming a gate electrode over the third gate dielectric layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first, second, and third gate dielectric layers comprise a same material.

### Claim 18 (depends on 16)

The method of claim 16, wherein after the removal process, the first gate dielectric layer contacts a portion of the well region.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
performing a planarization process on the gate electrode and on the first, second, and/or third gate dielectric layers, wherein after the planarization process, the gate electrode, the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer, and the substrate have substantially coplanar upper surfaces.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
forming a masking structure over outer portions of the first and second gate dielectric layers prior to the removal process, wherein the masking structure does not directly overlie the central portions of the first and second gate dielectric layers.