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US 2022/0102508 A1Published application
Integrated circuit structure and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorTze-Liang LEE
Life of this patent
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Abstract
A method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. A source/drain contact is formed over a source/drain region over the substrate. An etch stop layer is selectively formed over the dielectric cap such that the etch stop layer expose the source/drain contact. An interlayer dielectric is formed over the etch stop layer and the source/drain contact. A source/drain via is formed in the ILD and is connected to the source/drain contact.
Claims20
A method comprising:
- forming a gate structure over a substrate;
- forming a dielectric cap over the gate structure;
- forming a source/drain contact over a source/drain region next to the gate structure and over the substrate;
- selectively forming an etch stop layer over the dielectric cap without overlapping the source/drain contact;
- depositing an interlayer dielectric (ILD) layer over the etch stop layer and the source/drain contact;
- and
- forming a source/drain via extending through the ILD layer to the source/drain contact.
4 more elements
A device comprising:
- a source/drain contact over a source/drain region of a transistor;
- an etch stop layer over a gate structure of the transistor, wherein the etch stop layer has a step distance above the source/drain contact and a sidewall substantially aligned with a sidewall of the source/drain contact;
- an interlayer dielectric (ILD) layer above the etch stop layer;
- and
- a source/drain via extending through the ILD layer to the source/drain contact.
2 more elements
A device comprising:
- first and second source/drain contacts respectively over first and second source/drain regions of a transistor;
- an etch stop layer over a gate structure of the transistor;
- an interlayer dielectric (ILD) layer over the etch stop layer and having a stepped bottom surface having a lower step in contact with a top surface of the first source/drain contact and an upper step in contact with a top surface of the etch stop layer;
- and
- a via structure extending through the ILD layer and the etch stop layer to the gate structure.
2 more elements
Dependencies are inferred from the claim text.