Dual contact process with selective deposition

A complementary metal-oxide-semiconductor (CMOS), comprising:

• a first non-planar transistor of a first conductivity type, wherein the first non-planar transistor comprises:
• a first fin extending up from a substrate;
• a second fin extending up from the substrate;
• a first source region connecting the first fin to the second fin;
• a first drain region connecting the first fin to the second fin;
• a first interface material over the first source region and the first drain region;
• and
• first contacts connected to the first interface material over the first source region and the first drain region;
• and
• a second non-planar transistor of a second conductivity type that is opposite from the first conductivity type, wherein the second non-planar transistor comprises:
• a third fin extending up from the substrate;
• a fourth fin extending up from the substrate;
• a fifth fin extending up from the substrate;
• a second source region connecting the third fin, the fourth fin, and the fifth fin together;
• a second drain region connecting the third fin, the fourth fin, and the fifth fin together;
• a second interface material over the second source region and the second drain region;
• and
• second contacts connected to the first interface material over the second source region and the second drain region.

A method of forming a complementary metal-oxide-semiconductor (CMOS) device, comprising:

• providing a first non-planar transistor of a first conductivity type and a second non-planar transistor of a second conductivity type that is opposite from the first conductivity type, wherein the first non-planar transistor comprises a first source region and a first drain region, and wherein the second non-planar transistor comprises a second source region and a second drain region;
• depositing a first interface material over the first source region, the first drain region, the second source region, and the second drain region;
• depositing a protective layer over the first interface material;
• forming a mask over the first source region and the first drain region, wherein the second source region and the second drain region are exposed;
• removing the protective layer and the first interface material from the second source region and the second drain region;
• removing the mask;
• selectively depositing a second interface material over only the second source region and the second drain region;
• removing the protective layer;
• and
• depositing a contact metal over the first interface material and the second interface material.

An electronic device, comprising:

• a board;
• a package substrate attached to the board;
• and
• a die electrically coupled to the package substrate, wherein the die comprises a complimentary metal-oxide-semiconductor (CMOS) device, wherein the CMOS device comprises:
• a first transistor with a first interface material between a first source region and a first contact;
• and
• a second transistor with a second interface material between a second source region and a second contact.