Silicon carbide semiconductor device and power converter

A silicon carbide semiconductor device that includes a Schottky barrier diode in a field-effect transistor, the silicon carbide semiconductor device comprising:

• a semiconductor layer of a first conductivity type;
• a first semiconductor region of the first conductivity type provided in an upper layer portion of the semiconductor layer;
• a second semiconductor region of a second conductivity type provided with at least part of the second semiconductor region being in contact with a bottom face of the first semiconductor region and at least part of the second semiconductor region being provided in an upper layer portion of the semiconductor layer;
• a plurality of trenches provided in parallel with one another through the first semiconductor region and the second semiconductor region in a depth direction, and each having a bottom face that reaches inside the semiconductor layer;
• a gate electrode embedded in the plurality of trenches via a gate insulating film that covers inner faces of the plurality of trenches;
• an interlayer insulation film having a contact portion above the first semiconductor region;
• a first low-resistance layer of the first conductivity type provided in the semiconductor layer to have contact with at least one trench side walls of the plurality of trenches in a direction perpendicular to a direction of extension of the plurality of trenches;
• a Schottky barrier diode electrode provided on the semiconductor layer between each adjacent pair of the plurality of trenches;
• a second low-resistance layer of the first conductivity type provided in an upper layer portion of the semiconductor layer formed between each adjacent pair of the plurality of trenches to have contact with the Schottky barrier diode electrode;
• a first main electrode covering the interlayer insulation film and embedded in the contact portion;
• and
• a second main electrode provided on a main surface of the semiconductor layer on a side opposite to a side on which the first main electrode is provided,
• wherein the second semiconductor region provided in the upper layer portion of the semiconductor layer is provided to sandwich the second low-resistance layer between the adjacent pair of the plurality of trenches, and
• the second low-resistance layer has an impurity concentration higher than an impurity concentration of the semiconductor layer and lower than an impurity concentration of the first low-resistance layer.