Semiconductor device

A semiconductor device comprising:

• a substrate comprising a first region and a second region;
• a plurality of first channels on the first region apart from one another in a vertical direction;
• a plurality of second channels on the second region apart from one another in the vertical direction;
• a first gate structure contacting the plurality of first channels;
• a second gate structure contacting the plurality of second channels;
• a first gate spacer on at least one side surface of the first gate structure;
• a second gate spacer on at least one side surface of the second gate structure;
• a first source/drain structure contacting the plurality of first channels;
• and
• a second source/drain structure contacting the plurality of second channels,
• wherein a topmost portion of a bottom surface of the first gate spacer is lower than a topmost portion of a top surface of a topmost first channel from among the plurality of first channels, and
• wherein a topmost portion of a top surface of the first source/drain structure is lower than the topmost portion of the top surface of the topmost first channel.

A semiconductor device comprising:

• a substrate comprising a first region and a second region;
• a plurality of first channels on the first region apart from one another in a vertical direction;
• a plurality of second channels on the first region apart from one another in the vertical direction;
• a plurality of third channels on the second region apart from one another in the vertical direction;
• a plurality of fourth channels on the second region apart from one another in the vertical direction;
• a first gate structure contacting the plurality of first channels;
• a second gate structure contacting the plurality of second channels;
• a third gate structure contacting the plurality of third channels and the plurality of fourth channels;
• a first gate spacer on a side surface of the first gate structure;
• a second gate spacer on a side surface of the second gate structure;
• a third gate spacer on a side surface of the third gate structure;
• a first source/drain structure contacting the plurality of first channels;
• a second source/drain structure contacting the plurality of second channels;
• and
• a third source/drain structure contacting the plurality of third channels and the plurality of fourth channels,
• wherein a topmost portion of a bottom surface of the first gate spacer is lower than a topmost portion of a top surface of a topmost first channel from among the plurality of first channels, and
• a topmost portion of a top surface of the first source/drain structure is lower than the topmost portion of the top surface of the topmost first channel.