Device with epitaxial source/drain region
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShahaji B. More
Life of this patent
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Abstract
The present disclosure relates an integrated chip. The integrated chip may include a semiconductor substrate having sidewalls that define a plurality of fins. A dielectric material is arranged between the plurality of fins and a gate structure is disposed over the dielectric material and around the plurality of fins. Epitaxial source/drain regions are disposed along opposing sides of the gate structure and respectively include a plurality of source/drain segments disposed on the plurality of fins and a doped epitaxial material disposed onto and between the plurality of source/drain segments. A first source/drain segment of the plurality of source/drain segments laterally extends in opposing directions to different distances past opposing sides of an underlying first fin of the plurality of fins.
Claims20
An integrated chip, comprising:
- a semiconductor substrate comprising sidewalls that define a plurality of fins;
- a dielectric material arranged between the plurality of fins;
- a gate structure disposed over the dielectric material and around the plurality of fins;
- and
- epitaxial source/drain regions disposed along opposing sides of the gate structure and respectively comprising a plurality of source/drain segments disposed on the plurality of fins and a doped epitaxial material disposed onto and between the plurality of source/drain segments, wherein a first source/drain segment of the plurality of source/drain segments laterally extends in opposing directions to different distances past opposing sides of an underlying first fin of the plurality of fins.
An integrated chip, comprising:
- a semiconductor substrate comprising sidewalls that define a plurality of fins;
- a dielectric material arranged between the plurality of fins;
- a gate structure disposed over the dielectric material and around the plurality of fins;
- epitaxial source/drain regions disposed along opposing sides of the gate structure and over the plurality of fins, wherein the epitaxial source/drain regions comprise a first sidewall having a first height along a first side of a first fin of the plurality of fins and a second sidewall having a second height over along an opposing second side of the first fin, the first height different than the second height.
A method of forming an integrated chip, comprising:
- etching a semiconductor substrate to forming sidewalls of the semiconductor substrate that define a plurality of fins;
- forming a dielectric material between the plurality of fins;
- forming a gate structure over the dielectric material and around the plurality of fins;
- forming a fin spacer along sidewalls and an upper surface of the plurality of fins;
- etching the fin spacer to have a first sidewall with a first height along a first side of a first fin of the plurality of fins and to have a second sidewall with a second height along an opposing second side of the first fin, the first height greater than the second height;
- and
- forming epitaxial source/drain regions onto the plurality of fins and between sidewalls of the fin spacer.
Dependencies are inferred from the claim text.