Gate Oxide of Nanostructure Transistor with Increased Corner Thickness
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShu-Han Chen, Yi-Shao Li, Chun-Heng Chen, Chi On Chui
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Abstract
A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.
Claims20
A method comprising:
- epitaxially growing a plurality of semiconductor layers and a plurality of sacrificial layers alternatingly;
- patterning the plurality of semiconductor layers and the plurality of sacrificial layers to form a stack;
- removing a first portion and a second portion of the stack to form a first trench and a second trench, respectively;
- forming a first source/drain region and a second source/drain region in the first trench and the second trench, respectively, with a portion of the stack in between;
- removing the plurality of sacrificial layers from the portion of the stack;
- oxidizing the plurality of semiconductor layers in the portion of the stack to form gate oxides on the plurality of semiconductor layers, wherein the gate oxides comprise an oxide layer formed on a semiconductor layer in the plurality of semiconductor layers, and wherein the oxide layer comprises a horizontal portion and a vertical portion, and the vertical portion is thicker than the horizontal portion;
- and
- forming a gate electrode wrapping around the semiconductor layer and the oxide layer.
A device comprising:
- a semiconductor nanostructure;
- an oxide layer comprising:
- horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, wherein the horizontal portions have a first thickness;
- vertical portions on sidewalls of the semiconductor nanostructure, wherein the vertical portions have a second thickness;
- and
- corner portions on corners of the semiconductor nanostructure, wherein the corner portions have a third thickness, and wherein both of the second thickness and the third thickness are greater than the first thickness;
- a high-k dielectric layer surrounding the oxide layer;
- and
- a gate electrode surrounding the high-k dielectric layer.
A device comprising:
- a nano-FET comprising:
- a plurality of semiconductor strips, wherein higher ones of the plurality of semiconductor strips overlap corresponding lower ones of the plurality of semiconductor strips, and the plurality of semiconductor strips are vertically spaced apart from each other by spaces;
- a plurality of oxide layers, each wrapping around one of the plurality of semiconductor strips, wherein one of the plurality of oxide layers comprises:
- a first portion having a first thickness;
- and
- a second portion having a second thickness, wherein a ratio of the second thickness to the first thickness is greater than about 1.5.
Dependencies are inferred from the claim text.