Three-dimensional universal cmos device

A semiconductor device comprising:

• a universal device formed over a substrate, the universal device including a first source/drain (S/D) region formed over the substrate, a first channel region over the first S/D region, a second S/D region over the first channel region, and a first gate structure positioned between the first S/D region and the second S/D region and around the first channel region;
• and
• a transistor formed over the universal device, the transistor including a third S/D region positioned over the universal device, a second channel region over the third S/D region, a fourth S/D region over the second channel region, and a second gate structure positioned between the third S/D region and the fourth S/D region and around the second channel region, wherein:
• the universal device is one of a n-type transistor according to first applied bias voltages, and a p-type transistor according to second applied bias voltages.

A semiconductor device comprising:

• a first universal device formed over a substrate, the first universal device including a first source/drain (S/D) region over the substrate, a first channel region over the first S/D region, a second S/D region over the first channel region, and a first gate structure positioned between the first S/D region and the second S/D region and around the first channel region;
• an isolation structure positioned over the first universal device, the isolation structure further extending along a top surface of the substrate;
• a second universal device formed over the isolation structure and spaced apart from the first universal device by the isolation structure, the second universal device including a third S/D region over the isolation structure, a second channel region over the third S/D region, a fourth S/D region over the second channel region, and a second gate structure positioned between the third S/D region and the fourth S/D region and around the second channel region;
• and
• a salicide layer positioned between the first gate structure and the second gate structure, and further around the second S/D region and the third S/D region so that the second S/D region is coupled to the third S/D region, wherein:
• the first universal device is one of a first n-type transistor according to first applied bias voltages, and a first p-type transistor according to second applied bias voltages, and
• the second universal device is one of a second n-type transistor according to third applied bias voltages, and a second p-type transistor according to fourth applied bias voltages.

A method of manufacturing a semiconductor device, comprising:

• forming a stack of dielectric layers on a first layer of a semiconductor substrate, the stack of dielectric layers including layers made of at least three different dielectric materials with respective etch selectivity, an intermediate layer of the layers being made of one of the at least three different dielectric materials and disposed in a middle position of the stack of dielectric layers;
• forming an opening in the stack of dielectric layers such that the first layer of the semiconductor substrate is uncovered;
• epitaxially growing, within the opening, a channel material stack to form a vertical channel that extends from the first layer of the semiconductor substrate;
• etching the stack of dielectric layers to form a sidewall structure disposed along sidewalls of the vertical channel, the sidewall structure being formed of the layers of the at least three different dielectric materials;
• dividing the vertical channel into a lower channel and an upper channel that are isolated from one another;
• and
• forming a lower universal device based on the lower channel and an upper universal device based on the upper channel, wherein:
• the lower universal device is one of a first n-type transistor according to first bias voltages, and a first p-type transistor according to second bias voltages, and
• the upper universal device is one of a second n-type transistor according to third bias voltages, and a second p-type transistor according to fourth bias voltages.