Integrated circuit and method for fabricating the same

A method for fabricating an integrated circuit, comprising:

• depositing a etch stop layer over a dielectric layer, wherein the dielectric layer has a conductive feature therein;
• etching an opening in the etch stop layer to expose the conductive feature, such that the etch stop layer has a tapered sidewall adjoining the opening;
• depositing a bottom electrode layer into the opening in the etch stop layer;
• depositing a resistance switch layer over the bottom electrode layer;
• depositing a top electrode layer over the resistance switch layer;
• and
• patterning the top electrode layer, the resistance switch layer, and the bottom electrode layer into a memory structure comprising a bottom electrode, a resistance switch element over the bottom electrode, and a top electrode over the resistance switch element, such that the memory structure has a sidewall landing on the tapered sidewall of the etch stop layer.

An integrated circuit, comprising:

• a metal/dielectric layer having a first dielectric layer and a conductive feature in the first dielectric layer;
• a second dielectric layer over the metal/dielectric layer;
• a bottom electrode over the conductive feature and surrounded by the second dielectric layer, wherein the bottom electrode has a sidewall landing on a tapered sidewall of the second dielectric layer;
• a resistance switch element over the bottom electrode;
• and
• a top electrode over the resistance switch element.