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US 2022/0102393 A1Published application
Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHajime KIMURA
Life of this patent
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Abstract
It is an object to provide a semiconductor device which has a large size and operates at high speed. A top gate transistor which includes a semiconductor layer of single-crystal and a bottom gate transistor which includes a semiconductor layer of amorphous silicon (microcrystalline silicon) are formed over the same substrate. Then, gate electrodes of each transistor are formed with the same layer, and source and drain electrodes are also formed with the same layer. Thus, manufacturing steps are reduced. In other words, two types of transistors can be manufactured by adding only a few steps to the manufacturing process of a bottom gate transistor.
Claims9
A display device comprising:
- a first semiconductor layer;
- a second semiconductor layer;
- a third semiconductor layer;
- a first insulating layer;
- and
- a second insulating layer,
- wherein the first conductive layer comprises a channel formation region of the first transistor,
- wherein the second semiconductor layer and the third semiconductor layer are provided in a same layer and comprise an oxide semiconductor,
- wherein the first insulating layer is provided over the first semiconductor layer and under the second semiconductor layer and the third semiconductor layer, the first insulating layer comprising silicon nitride,
- wherein the second semiconductor layer comprises a channel formation region of a second transistor,
- wherein the third semiconductor layer does not comprise a channel formation region of a transistor,
- wherein a gate electrode of the first transistor is provided over the first semiconductor layer,
- wherein a gate electrode of the second transistor is provided under the second semiconductor layer,
- wherein the gate electrode of the first transistor and the gate electrode of the third transistor are in contact with a bottom surface of the first insulating layer,
- wherein the first insulating layer has a region functioning as a gate-insulating layer of the second transistor,
- wherein the gate electrode of the first transistor and the gate electrode of the second transistor are in contact with a top surface of the second insulating layer,
- wherein the second insulating layer has a region functioning as a gate-insulating layer of the first transistor,
- wherein the third semiconductor layer is in contact with a bottom surface of a first wiring layer electrically connected to the first transistor,
- wherein a second wiring layer is provided in a same layer as the first wiring layer, and
- wherein the second wiring layer does not have a region overlapping with a semiconductor layer provided in the same layer as the second semiconductor layer.
17 more elements
A display device comprising:
- a first semiconductor layer;
- a second semiconductor layer;
- a third semiconductor layer;
- a first insulating layer;
- and
- a second insulating layer,
- wherein the first semiconductor layer comprises polycrystalline silicon,
- wherein the first conductive layer comprises a channel formation region of the first transistor,
- wherein the second semiconductor layer and the third semiconductor layer are provided in a same layer and comprise an oxide semiconductor,
- wherein the first insulating layer is provided over the first semiconductor layer and under the second semiconductor layer and the third semiconductor layer, the first insulating layer comprising silicon nitride,
- wherein the second semiconductor layer comprises a channel formation region of a second transistor,
- wherein the third semiconductor layer does not comprise a channel formation region of a transistor,
- wherein a gate electrode of the first transistor is provided over the first semiconductor layer,
- wherein a gate electrode of the second transistor is provided under the second semiconductor layer,
- wherein the gate electrode of the first transistor and the gate electrode of the third transistor are in contact with a bottom surface of the first insulating layer,
- wherein the first insulating layer has a region functioning as a gate-insulating layer of the second transistor,
- wherein the gate electrode of the first transistor and the gate electrode of the second transistor are in contact with a top surface of the second insulating layer,
- wherein the second insulating layer has a region functioning as a gate-insulating layer of the first transistor,
- wherein the third semiconductor layer is in contact with a bottom surface of a first wiring layer electrically connected to the first transistor,
- wherein a second wiring layer is provided in a same layer as the first wiring layer, and
- wherein the second wiring layer does not have a region overlapping with a semiconductor layer provided in the same layer as the second semiconductor layer.
18 more elements
A display device comprising:
- a first semiconductor layer;
- a second semiconductor layer;
- a third semiconductor layer;
- a first insulating layer;
- and
- a second insulating layer,
- wherein the first semiconductor layer comprises single-crystal silicon,
- wherein the first conductive layer comprises a channel formation region of the first transistor,
- wherein the second semiconductor layer and the third semiconductor layer are provided in a same layer and comprise an oxide semiconductor,
- wherein the first insulating layer is provided over the first semiconductor layer and under the second semiconductor layer and the third semiconductor layer, the first insulating layer comprising silicon nitride,
- wherein the second semiconductor layer comprises a channel formation region of a second transistor,
- wherein the third semiconductor layer does not comprise a channel formation region of a transistor,
- wherein a gate electrode of the first transistor is provided over the first semiconductor layer,
- wherein a gate electrode of the second transistor is provided under the second semiconductor layer,
- wherein the gate electrode of the first transistor and the gate electrode of the third transistor are in contact with a bottom surface of the first insulating layer,
- wherein the first insulating layer has a region functioning as a gate-insulating layer of the second transistor,
- wherein the gate electrode of the first transistor and the gate electrode of the second transistor are in contact with a top surface of the second insulating layer,
- wherein the second insulating layer has a region functioning as a gate-insulating layer of the first transistor,
- wherein the third semiconductor layer is in contact with a bottom surface of a first wiring layer electrically connected to the first transistor,
- wherein a second wiring layer is provided in a same layer as the first wiring layer, and
- wherein the second wiring layer does not have a region overlapping with a semiconductor layer provided in the same layer as the second semiconductor layer.
18 more elements
Dependencies are inferred from the claim text.