Semiconductor memory device and method of manufacturing the same

A semiconductor memory device comprising:

• a stack with a plurality of interlayer insulating layers and gate electrodes alternately stacked on a substrate;
• and
• a plurality of channel structures passing through the stack in a vertical direction,
• wherein each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures,
• at least one first gate electrode that is disposed at an uppermost portion of the gate electrodes corresponds to a drain select transistor, at least one second gate electrode that is disposed at a lowermost portion of the gate electrodes corresponds to a source select transistor, and remaining gate electrodes among the electrodes correspond to the memory cells, and
• a partial region of the core insulating layer that is adjacent to the first gate electrode or the second gate electrode has a dielectric constant that is lower than a dielectric constant of another region that is adjacent to the remaining gate electrodes.

A method of manufacturing a semiconductor memory device, the method comprising:

• forming a stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate;
• forming a plurality of holes that pass through the stack in a vertical direction;
• sequentially forming a charge storage layer, a tunnel insulating layer, and a channel layer on sidewalk of each of the plurality of holes;
• forming a core insulating layer on a sidewall of the channel layer to fill center regions of the plurality of holes;
• and
• injecting a dopant into a partial region so that a dielectric constant of the partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.

A method of manufacturing a semiconductor memory device, the method comprising:

• forming a stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate;
• forming a plurality of holes that pass through the stack in a vertical direction;
• sequentially forming a charge storage layer, a tunnel insulating layer, and a channel layer on sidewalls of each of the plurality of holes;
• and
• forming a core insulating layer on a sidewall of the channel layer to fill a center region of the plurality of holes,
• wherein forming the core insulating layer comprises forming a gap in a partial region of the core insulating layer.