Back to results
US 2022/0102369 A1Published application
Semiconductor device and data storage system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsGiyong CHUNG, Jaeryong SIM, Kwangyoung JUNG, Jeehoon HAN
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.
Claims20
A semiconductor device comprising:
- a peripheral circuit region including a first substrate and a plurality of circuit elements on the first substrate;
- and
- at least one memory cell region on the peripheral circuit region,
- wherein the at least one memory cell region includes:
- a second substrate on the peripheral circuit region;
- a memory stack structure including a first stack structure and a second stack structure, the first stack structure including a plurality of first gate electrodes and a plurality of first interlayer insulating layers alternately stacked on the second substrate, and the second stack structure including a plurality of second gate electrodes and a plurality of second interlayer insulating layers alternately stacked on the first stack structure;
- a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate, the plurality of channel structures each including a respective channel layer;
- at least one first dummy structure on the second substrate, the at least one first dummy structure spaced apart from at least one side of the first stack structure, and the at least one first dummy structure including a plurality of first insulating layers and a plurality of second insulating layers alternately stacked;
- at least one second dummy structure on the at least one first dummy structure, the at least one second dummy structure spaced apart from at least one side of the second stack structure, the at least one second dummy structure including a plurality of third insulating layers and a plurality of fourth insulating layers alternately stacked;
- and
- at least a portion of the at least one first dummy structure does not overlap the at least one second dummy structure in a vertical direction.
8 more elements
A semiconductor device comprising:
- a peripheral circuit region including a first substrate and a plurality of circuit elements provided on the first substrate;
- a second substrate on the peripheral circuit region;
- a memory cell structure on the second substrate;
- and
- a dummy structure on at least one side of the memory cell structure, the dummy structure on the second substrate,
- wherein the memory cell structure includes:
- a first stack structure including a plurality of first gate electrodes and a plurality of first interlayer insulating layers alternately stacked on the second substrate;
- a second stack structure including a plurality of second gate electrodes and a plurality of second interlayer insulating layers alternately stacked on the first stack structure;
- and
- a plurality of channel structures penetrating through the first stack structure and the second stack structure, the plurality of channel structures connected to the second substrate, and
- wherein the dummy structure includes:
- a first dummy structure on the second substrate, the first dummy structure spaced apart from the first stack structure, and the first dummy structure including a plurality of first insulating layers and a plurality of second insulating layers alternately stacked;
- and
- a second dummy structure on the second substrate, the second dummy structure spaced apart from the second stack structure and the first dummy structure, the second dummy structure including a plurality of third insulating layers and a plurality of fourth insulating layers alternately stacked, and
- wherein a central axis between side surfaces of the second dummy structure is shifted from a central axis between side surfaces of the first dummy structure in at least one direction parallel to an upper surface of the second substrate.
12 more elements
A data storage system comprising:
- a semiconductor storage device including a peripheral circuit region including a first substrate and circuit elements provided on the first substrate, a second substrate on the peripheral circuit region, a memory cell structure on the second substrate, a dummy structure on at least one side of the memory cell structure and on the second substrate;
- and
- a controller electrically connected to the semiconductor storage device through a input/output pad and controlling the semiconductor storage device,
- wherein the memory cell structure includes:
- a first stack structure including a plurality of first gate electrodes and a plurality of first interlayer insulating layers alternately stacked on the second substrate;
- a second stack structure including a plurality of second gate electrodes and a plurality of second interlayer insulating layers alternately stacked on the first stack structure;
- and
- a plurality of channel structures penetrating through the first stack structure and the second stack structure, the plurality of channel structures connected to the second substrate,
- wherein the dummy structure includes:
- a first dummy structure spaced apart from the first stack structure and on the second substrate;
- and
- a second dummy structure on the second substrate, the second dummy structure spaced apart from the second stack structure and the first dummy structure, and
- wherein a central axis between side surfaces of the second dummy structure is shifted from a central axis between side surfaces of the first dummy structure in at least one direction parallel to an upper surface of the second substrate.
10 more elements
Dependencies are inferred from the claim text.