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US 2022/0102365 A1Published application
Asymmetric junctions of high voltage transistor in nand flash memory
AssigneeIntel Corporation
InventorsChang Wan HA, Chuan LIN, Deepak THIMMEGOWDA, Zengtao LIU, Binh N. NGO, Soo-yong PARK
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Abstract
The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.
Claims19
A non-volatile memory device comprising:
- a memory array, the memory array including a plurality of global word lines;
- and
- a plurality of high voltage transistors to couple to one of the plurality of global word lines, the high voltage transistor including a gate, a source and a drain, the drain coupled to the one of the plurality of global word lines, a source silicon area dependent on a maximum source voltage applied to the source and a drain silicon area dependent on a maximum drain voltage applied to the drain.
A system comprising:
- a memory controller;
- and
- a non-volatile memory device coupled with the memory controller, the non-volatile memory device comprising:
- a memory array, the memory array including a plurality of global word lines;
- and
- a plurality of high voltage transistors to couple to one of the plurality of global word lines, the high voltage transistor including a gate, a source and a drain, the drain coupled to the one of the plurality of global word lines, a source silicon area dependent on a maximum source voltage applied to the source and a drain silicon area dependent on a maximum drain voltage applied to the drain.
3 more elements
Dependencies are inferred from the claim text.