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US 2022/0102364 A1Published application
Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsHee Bum HONG, Yongrae CHO
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Abstract
Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.
Claims20
A semiconductor memory device, comprising:
- a plurality of memory cells on a substrate, each of the plurality of memory cells including an access transistor and a pull-down transistor;
- a first line layer on the memory cells, the first line layer including a power line, a first lower landing pad, and a second lower landing pad;
- a second line layer on the first line layer, the second line layer including a ground line having an opening, an upper landing pad in the opening, and vias provided below the ground line and the upper landing pad, the opening surrounding the upper landing pad when viewed in a plan view, the ground line including a pair of first segments and a pair of second segments that define the opening, each of the first segments extending in a first direction and having a first width in a second direction intersecting the first direction, each of the second segments extending in the second direction and having a second width in the first direction;
- and
- a third line layer including a word line on the second line layer,
- wherein the ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor, and
- wherein the word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor,
- wherein the power line vertically overlaps a corresponding one of the first segments,
- wherein both sidewalls of the power line vertically overlap the corresponding one of the first segments such that a third width of the power line is less than or equal to the first width,
- wherein the vias below the ground line are connected only to the second segments and not to the first segments.
7 more elements
A semiconductor memory device, comprising:
- a plurality of memory cell transistors on a substrate;
- a first line layer on the memory cell transistors;
- and
- a second line layer on the first line layer,
- wherein the first line layer includes a bit line, a power line, a first lower landing pad, and a second lower landing pad,
- wherein the second line layer includes a ground line having a plurality of openings,
- wherein the ground line includes a pair of first segments that extend in a first direction and a pair of second segments that extend in a second direction intersecting the first direction,
- wherein each of the openings is defined by the pair of first segments and the pair of second segments,
- wherein the second line layer further includes first vias provided below the ground line,
- wherein the first vias are connected only to the second segments and not to the first segments,
- wherein the power line vertically overlaps a corresponding one of the first segments,
- wherein both sidewalls of the power line vertically overlap the corresponding one of the first segments such that a width of the power line is less than or equal to a width of the corresponding one of the first segments, and
- wherein the ground line has electrical connection through the first vias and the first lower landing pad to a terminal of a first memory transistor of the memory cell transistors.
10 more elements
A semiconductor memory device, comprising:
- a plurality of memory cells on a substrate, each of the memory cells including a plurality of memory transistors;
- and
- a first line layer, a second line layer, and a third line layer sequentially stacked on the memory cells,
- wherein the first line layer includes a bit line, a power line, and a first lower landing pad,
- wherein the second line layer includes a ground line having an opening, an upper landing pad in the opening, and vias provided below the ground line and the upper landing pad, the ground line including a pair of first segments and a pair of second segments that define the opening, each of the first segments extending in a first direction and having a first width in a second direction intersecting the first direction, each of the second segments extending in the second direction and having a second width in the first direction, the first width being different from the second width,
- wherein the opening surrounds the upper landing pad when viewed in a plan view,
- wherein the third line layer includes a word line,
- wherein the word line is electrically connected through the upper landing pad and the first lower landing pad to a terminal of a first memory transistor of the memory transistors,
- wherein the power line vertically overlaps a corresponding one of the first segments, and
- wherein the vias below the ground line are connected only to the second segments and not to the first segments.
7 more elements
Dependencies are inferred from the claim text.