Semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYou-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
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Abstract
A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.
Claims20
A semiconductor device, comprising:
- at least one memory cell;
- and
- at least one logic cell disposed next to the at least one memory cell, comprising:
- a plurality of fins, wherein the plurality of fins are separated into a plurality of fin groups for forming transistors,
- wherein a distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.
A semiconductor device, comprising:
- a memory cell having a cell height, comprising:
- a plurality of first fins extending along a first direction;
- and
- a logic cell abutting to the memory cell and having the cell height, comprising:
- a plurality of second fins extending along the first direction based on the cell height and a plurality of fin grids that extend along the first direction, wherein each adjacent two of the plurality of fin grids have a fin pitch therebetween,
- wherein at least one of the plurality of second fins is substantially aligned with at least one of the plurality of first fins, and at least one of the plurality of second fins is not aligned with the plurality of fin grids.
A method of fabricating an integrated circuit (IC), comprising:
- in a logic cell disposed next to a memory cell,
- forming at least three fin groups that are separate from each other and extend along a first direction, within a cell height of the logic cell that is equal to a cell height of the memory cell in a layout view, for forming corresponding transistors in the integrated circuit.
Dependencies are inferred from the claim text.