Cfet sram bit cell with two stacked device decks

A static random access memory (SRAM), comprising:

• a plurality of SRAM bit cells on a substrate, each SRAM bit cell comprising:
• at least six transistors including at least two NMOS transistors and at least two PMOS transistors;
• each of the at least six transistors being lateral transistors with channels formed from nano-sheets grown by epitaxy;
• the at least six transistors positioned in two decks in which a second deck is positioned vertically above a first deck relative to a working surface of the substrate, wherein at least one NMOS transistor and at least one PMOS transistor share a common vertical gate;
• a first inverter formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck;
• a second inverter formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck;
• and
• a pass gate located in either the first deck or the second deck.

A method for forming a static random access memory (SRAM) bit cell on a substrate, the method comprising:

• forming at least six transistors including at least two NMOS transistors and at least two PMOS transistors, each of the six transistors being lateral transistors with channels formed from nano-sheets grown by epitaxy, the at least six transistors positioned in two decks in which a second deck is positioned vertically above a first deck relative to a working surface of the substrate, wherein at least one NMOS transistor and at least one PMOS transistor share a common vertical gate;
• forming a first inverter using a first transistor positioned in the first deck and a second transistor positioned in the second deck;
• forming a second inverter formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck;
• and
• forming a pass gate located in either the first deck or the second deck.