US 2022/0102360 A1 · STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELL CIRCUITS WITH A MINIMUM DISTANCE BETWEEN A STORAGE CIRCUIT ACTIVE REGION AND A READ PORT CIRCUIT ACTIVE REGION TO REDUCE AREA AND SRAM BIT CELL ARRAY CIRCUITS

Abstract

SRAM cell circuits have a minimum distance between a storage circuit active region and a read port circuit active region to reduce area. SRAM cell circuits are formed in FinFETs in a storage circuit active area and a read port active area each including one or more diffusion regions of a substrate. Design rule constraints limit a minimum center-to-center distance between adjacent parallel fins. The SRAM bit cell has a reduced total area because a distance between the storage circuit active area and the read port active area is reduced to a minimum separation distance of between 1.0 and 2.15 times the smallest center-to-center distance between adjacent fins. Minimizing a separation distance may include relocating a gate contact of a write access transistor from a location between the storage circuit active region and the read port active region to a location overlapping the storage circuit active area.

Claims21

Dependent claims

A memory bit cell circuit comprising:

a substrate;
a first plurality of fins extending in a first direction on the substrate, wherein a smallest center-to-center distance from a first fin to a nearest adjacent fin of the first plurality of fins, in a second direction orthogonal to the first direction, is a minimum fin pitch;
a storage circuit configured to store a data value, the storage circuit comprising a storage circuit active area of the substrate, the storage circuit active area comprising a first subset of the first plurality of fins;
a read port circuit configured to read the data value, the read port circuit comprising a read port active area of the substrate, the read port active area comprising a second subset of the first plurality of fins;
and
an inactive area between the storage circuit active area and the read port active area,
wherein a width of the inactive area in the second direction from the storage circuit active area to the read port active area is between 1.0 and 2.15 times the minimum fin pitch.

4 more elements

A memory bit cell array circuit comprising:

a substrate;
a first memory bit cell circuit comprising:
a first plurality of fins extending in a first direction on the substrate, wherein a smallest center-to-center distance from a first fin to a nearest adjacent fin of the first plurality of fins, in a second direction orthogonal to the first direction, is a minimum fin pitch;
a first storage circuit configured to store a first data value, the first storage circuit comprising a first storage circuit active area of the substrate, the first storage circuit active area comprising a first subset of the first plurality of fins;
and
a first read port circuit configured to read the first data value, the first read port circuit comprising a first read port active area of the substrate, the first read port active area comprising a second subset of the first plurality of fins,
wherein the first read port circuit is on a first side of the first storage circuit in the second direction;
a second memory bit cell circuit comprising:
a second plurality of fins extending in the first direction on the substrate;
a second storage circuit configured to store a second data value, the second storage circuit comprising a second storage circuit active area of the substrate, the second storage circuit active area comprising a first subset of the second plurality of fins;
and
a second read port circuit configured to read the second data value, the second read port circuit comprising a second read port active area of the substrate, the second read port active area comprising a second subset of the second plurality of fins,
wherein the second read port circuit is on a second side of the second storage circuit in the second direction;
and
an inactive array area between the first read port circuit and the second read port circuit, wherein a width of the inactive array area from the first read port active area to the second read port active area is between 1.0 and 2.15 times the minimum fin pitch.

12 more elements

A method of making a memory bit cell array circuit, the method comprising:

forming a substrate;
forming a first memory bit cell circuit comprising:
a first plurality of fins extending in a first direction on the substrate, wherein a smallest center-to-center distance from a first fin to a nearest adjacent fin of the first plurality of fins, in a second direction orthogonal to the first direction, is a minimum fin pitch;
a first storage circuit configured to store a first data value, the first storage circuit comprising a first storage circuit active area of the substrate, the first storage circuit active area comprising a first subset of the first plurality of fins;
and
a first read port circuit configured to read the first data value, the first read port circuit comprising a first read port active area of the substrate, the first read port active area comprising a second subset of the first plurality of fins,
wherein the first read port circuit is on a first side of the first storage circuit in the second direction;
forming a second memory bit cell circuit comprising:
a second plurality of fins extending in the first direction on the substrate;
a second storage circuit configured to store a second data value, the second storage circuit comprising a second storage circuit active area of the substrate, the second storage circuit active area comprising a first subset of the second plurality of fins;
and
a second read port circuit configured to read the second data value, the second read port circuit comprising a second read port active area of the substrate, the second read port active area comprising a second subset of the second plurality of fins,
wherein the second read port circuit is on a second side of the second storage circuit in the second direction;
and
forming an inactive array area between the first read port circuit and the second read port circuit, wherein a width of the inactive array area from the first read port active area to the second read port active area is between 1.0 and 2.15 times the minimum fin pitch.

12 more elements

Dependencies are inferred from the claim text.

Static random access memory (sram) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and sram bit cell array circuits

Life of this patent

Static random access memory (sram) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and sram bit cell array circuits

Life of this patent

Abstract

Claims21