Semiconductor memory device

A semiconductor memory device comprising:

• at least one bit line on a semiconductor substrate, the at least one bit line extending in a first direction perpendicular to a top surface of the semiconductor substrate;
• at least one gate electrode including an upper gate electrode and a lower gate electrode extending in a second direction parallel to the top surface of the semiconductor substrate, the upper gate electrode being spaced apart from the lower gate electrode in the first direction;
• at least one semiconductor pattern between the lower gate electrode and the upper gate electrode and extending in a third direction different from the first direction and the second direction, a portion of the at least one semiconductor pattern overlapping the upper gate electrode and the lower gate electrode in the third direction;
• and
• at least one information storage element connected to the at least one semiconductor pattern.

A semiconductor memory device comprising:

• a plurality of mold insulating layers on a semiconductor substrate which are spaced apart from each other in a first direction perpendicular to a top surface of the semiconductor substrate;
• a plurality of semiconductor patterns between the plurality of mold insulating layers, the plurality of semiconductor patterns adjacent to each other in the first direction;
• a plurality of gate electrodes on each of the plurality of semiconductor patterns, the plurality of gate electrodes between the plurality of mold insulating layers, the plurality of gate electrodes adjacent to each other in the first direction and extending in a second direction perpendicular to the first direction, each of the gate electrodes including an upper gate electrode and a lower gate electrode spaced apart in the first direction;
• a bit line on the semiconductor substrate, the bit line extending in the first direction and being connected to the plurality of semiconductor patterns;
• and
• a capacitor structure connected to the plurality of semiconductor patterns,
• wherein each of the semiconductor patterns includes a horizontal portion extending in a third direction different from the first direction and the second direction, and a vertical portion extending in the first direction,
• a first end of the horizontal portion of each of the semiconductor patterns is connected to the bit line, and a second end of the horizontal portion of each of the semiconductor patterns is connected to the vertical portion of the semiconductor pattern, and
• a thickness of the horizontal portion of each of the semiconductor patterns in the first direction is smaller than a thickness of the vertical portion of each of the semiconductor patterns in the first direction.