Bitline structure for three-dimensional integrated circuit and method of forming the same

A method of manufacturing a bonded semiconductor structure, comprising:

• providing a support substrate which carries circuitry;
• providing a first multiple bypass bitline which includes an upper bypass interconnect and a plurality of upper bypass vias;
• providing a first conductive bonding layer, wherein the first conductive bonding layer is connected to the upper bypass interconnect through the plurality of upper bypass vias;
• and
• providing a first plurality of vertical transistors carried by the first conductive bonding layer, the first plurality of vertical transistors being in communication with the circuitry, wherein the circuitry provides memory operation;
• wherein the plurality of upper bypass vias electrically connect the first conductive bonding layer and the upper bypass interconnect in parallel with each other.

A method of forming a bonded semiconductor structure, comprising:

• providing a support substrate which carries circuitry;
• providing a first and second multiple bypass bitlines which each include upper and lower bypass interconnects;
• providing first and second conductive bonding layers connected to the first and second multiple bypass interconnects, respectively;
• and
• providing first and second vertical transistors carried by the first and second conductive bonding layers, respectively, the first and second vertical transistors being controlled by the circuitry.