Epitaxial single crystalline silicon growth for a horizontal access device

A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:

• depositing layers of a first dielectric material, a second dielectric material, and a third dielectric material, in repeating iterations vertically to form a vertical stack;
• forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack;
• conformally depositing a first conductive material on a gate dielectric material in the plurality of first vertical openings;
• removing portions of the first conductive material in the plurality of first vertical openings to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns;
• forming a second vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose second vertical sidewalls adjacent first region of the second dielectric material;
• selectively removing first portions of the second dielectric material a first distance (DIST 1) from the second vertical opening to form first horizontal openings in the second dielectric material;
• depositing a polysilicon material in the first horizontal openings;
• forming third vertical openings through the vertical stack and extending predominantly in the first horizontal direction to expose third vertical sidewalls adjacent a second region of the second dielectric material;
• selectively removing second portions of the second dielectric material a second distance (DIST 2) from the third vertical openings to the deposited polysilicon material to form second horizontal openings in the second horizontal direction having the deposited polysilicon at a distal end of the second horizontal openings from the third vertical openings;
• and
• epitaxially growing single crystalline silicon within the second horizontal openings from the distal end of the second horizontal openings toward the third vertical openings to fill the second horizontal openings.

A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:

• depositing layers of a first dielectric material, a second dielectric material, and a third dielectric material, in repeating iterations vertically to form a vertical stack;
• forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack;
• conformally depositing a first conductive material on a gate dielectric material in the plurality of first vertical openings;
• removing portions of the first conductive material in the plurality of first vertical openings to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns;
• forming a second vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose second vertical sidewalls adjacent a first region of the second dielectric material;
• forming a third vertical opening through the vertical stack and a portion of a substrate extending predominantly in the first horizontal direction to expose third vertical sidewalls adjacent a second region of the second dielectric material;
• epitaxially growing single crystalline silicon from the substrate within the third vertical openings;
• selectively removing the second dielectric material to form first horizontal openings;
• and
• epitaxially growing single crystalline silicon within the first horizontal openings from the single crystalline silicon in the third vertical openings toward the second vertical opening to fill the first horizontal openings.

A memory device, comprising:

• an array of vertically stacked memory cells, the array having horizontally oriented access devices and digit lines and vertically oriented access lines, comprising:
• the horizontally oriented access devices having a first source/drain region and a second source drain region separated by an epitaxially grown single crystalline channel and body region, and having gates opposing the channel region and separated therefrom by a gate dielectric;
• the vertically oriented access lines coupled to the gates and separated from the channel region by the gate dielectric;
• the horizontally oriented storage nodes electrically coupled to the second source/drain regions of the horizontally oriented access devices;
• and
• the horizontally oriented digit lines electrically coupled to the first source/drain regions of the horizontally oriented access devices.