Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsKiseok LEE, Kyunghwan LEE, Dongoh KIM, Yongseok KIM, Hui-jung KIM, Min Hee CHO
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Abstract
A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.
Claims21
A semiconductor memory device, comprising:
- a bit line extending in a first direction;
- a channel pattern on the bit line, the channel pattern comprising a first vertical portion and a second vertical portion facing each other and a horizontal portion connecting the first vertical portion with the second vertical portion;
- a first word line and a second word line provided on the horizontal portion and between the first vertical portion and the second vertical portion, the first word line and the second word line extending in a second direction crossing the bit line;
- and
- a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.
A semiconductor memory device, comprising:
- a peripheral circuit structure comprising a plurality of peripheral circuits on a semiconductor substrate and a lower insulating layer covering the plurality of peripheral circuits;
- a plurality of bit lines extended in a first direction on the peripheral circuit structure;
- a first insulating pattern defining a trench, the first insulating pattern crossing the plurality of bit lines and extending in a second direction;
- a plurality of channel patterns provided in the trench and spaced apart from each other in the second direction, each of the plurality of channel patterns comprising a first vertical portion and a second vertical portion facing each other and a horizontal portion connecting the first vertical portion with the second vertical portion;
- a first word line and a second word line provided on the horizontal portion of each of the plurality of channel patterns, the first word line and the second word line extending in the second direction, the first word line being adjacent to the first vertical portion of each of the plurality of channel patterns, the second word line being adjacent to the second vertical portion of each of the plurality of channel patterns;
- for each of the plurality of channel patterns, a gate insulating pattern extending in the second direction disposed between the channel pattern and the first word line and between the channel pattern and the second word line;
- a second insulating pattern covering the first word line and the second word line in the trench;
- a plurality of first data storage patterns disposed on respective first vertical portions of the plurality of channel patterns;
- and
- a plurality of second data storage patterns disposed on respective second vertical portions of the plurality of channel patterns.
A semiconductor memory device, comprising:
- a bit line extending in a first direction;
- a channel pattern on the bit line, the channel pattern comprising a first vertical portion and a second vertical portion facing each other and a horizontal portion connecting the first vertical portion and the second vertical portion;
- a first word line extending in a second direction to cross the bit line, the first word line being disposed on the horizontal portion and between the first vertical portion and the second vertical portion;
- and
- a gate insulating pattern interposed between the first word line and the channel pattern.
21-22. (canceled)
Dependencies are inferred from the claim text.