Integrated Circuitry, Memory Circuitry, Method Used In Forming Integrated Circuitry, And Method Used In Forming Memory Circuitry

A method used in forming memory circuitry, comprising:

• forming conductive material over a substrate;
• patterning the conductive material into multiple conductive lines that are horizontally longitudinally elongated and laterally spaced from one another;
• vertically recessing the conductive material in longitudinally-spaced first regions of individual of the conductive lines to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the individual conductive lines, the conductive pillars projecting vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the individual conductive lines;
• forming vertical transistors directly above the conductive pillars;
• individual of the vertical transistors comprising a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions;
• the bottom source/drain region being directly above and directly against individual of the conductive pillars;
• and
• forming a storage device directly above and directly electrically coupled to the top source/drain region.

Integrated circuitry, comprising:

• a conductive line that is horizontally longitudinally elongated, the conductive line comprising longitudinally-spaced first regions that alternate with longitudinally-spaced second regions along the conductive line, the longitudinally-spaced second regions being characterized by a conductive pillar that projects vertically relative to conductive material of the conductive line in the longitudinally-spaced first regions;
• the conductive pillar having an uppermost conductive surface and the conductive material of the conductive line in individual of the longitudinally-spaced first regions having an uppermost conductive surface;
• the uppermost conductive surface of the conductive pillar having a maximum length in a straight-line direction that is orthogonal to longitudinal orientation of the conductive line that is shorter than a maximum length of the uppermost conductive surface of the conductive material of the conductive line in the individual longitudinally-spaced first regions in the straight-line direction;
• and
• electronic components directly above the conductive pillars, individual of the electronic components being directly electrically coupled to individual of the conductive pillars.

Memory circuitry comprising:

• multiple conductive lines that are horizontally longitudinally elongated and laterally spaced from one another, individual of the conductive lines comprising longitudinally-spaced first regions that alternate with longitudinally-spaced second regions along the individual conductive line, the longitudinally-spaced second regions being characterized by a conductive pillar that projects vertically relative to conductive material of the respective individual conductive line in the longitudinally-spaced first regions;
• the conductive pillar having an uppermost conductive surface and the conductive material of the conductive line in individual of the longitudinally-spaced first regions having an uppermost conductive surface;
• the uppermost conductive surface of the conductive pillar having a maximum length in a straight-line direction that is orthogonal to longitudinal orientation of the conductive line that is shorter than a maximum length of the uppermost conductive surface of the conductive material of the respective conductive line in the individual longitudinally-spaced first regions in the straight-line direction;
• vertical transistors directly above the conductive pillars;
• individual of the vertical transistors comprising a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions;
• the bottom source/drain region being directly above and directly against individual of the conductive pillars;
• and
• a storage device directly above and directly electrically coupled to the top source/drain region.